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Delta Sheet
DS7, 2002-09-16 QuadFALC(R) Quad E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications PEF 22554 HT Version 2.1 PEF 22554 E Version 2.1
Preface This document describes the changes implemented in the QuadFALC(R) Version 2.1 related to the previous version 1.3. All functions not mentioned in this document remain unchanged. QuadFALC(R) Version 2.1 is a pin-compatible replacement of QuadFALC(R) Version 1.x. Severe errata of QuadFALC(R) Version 1.3 are fixed. For more information please contact your local sales office. Organization of this Document * * * * Chapter 1, Overview Gives a general description of the product differences to its predecessor. Chapter 2, Electrical Characteristics Shows the differences in electrical behavior. Chapter 2.4, Changed Supply Power Test Conditions T1/J1 Shows the mechanical dimensions of the new BGA package. Chapter 3, Appendix Shows a screenshot of the available software tool.
Related Documentation Data Sheet PEF 22554 Version 2.1 Errata Sheet PEB 22554 Version 1.3 Addendum PEB 22554 Version 1.3
Revision History: Previous Version: Preliminray Delta Sheet DS 6, 2002-08-19 Major Changes: "Functional Changes" on Page 2: Additional compare status field (CCR5.6) "Changed DC Characteristics" on Page 26: Power Supply Currents & LOS Limits,
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QuadFALC(R) PEF 22554
Overview
1
1.1
* * * * * * * * *
Overview
Functional Changes
The following function has been changed: Version status in register VSTR changed from 02H to 05H The boundary scan part number changed to 142, the boundary scan ID changed to 1. A new BSDL file is required. The pulse mask programming (registers XPM(2:0)) has to be adjusted. The MCLK reference clock programming (registers GCM(8:1)) has to be changed. Variable master clock frequency function always enabled (GCM2(4) = 1). New feature "automatic short haul/long haul adjustment" available by setting LIM0.EQON = 1. Additional automatic resynchronization mode for T1 (new bit: FMR2.7 = AFRS). Additional compare status field (mode 2) in SS7 mode (new bit: CCR5.6 = CSF2). 2048 kHz synchronization interface according o ITU-T G.703 Sec. 13 (E1). For more information refer to online Application Notes http://www.infineon.com/falc.
1.2
Correction of Errata
All severe errata of QuadFALC(R) Version 1.3 have been fixed. For more information please contact your local sales office.
1.3
Modified Pin Functions
QuadFALC(R) Version 2.1 is pin-compatible with QuadFALC(R) Version 1.x. However, some pin functions have been modified as detailed below: * * No 5 V input levels are allowed due to technology restrictions (see Page 24). The currently unused ("N.C.") pins on V1.3 devices are used as "Core Voltage Supply" (VDDC) pins and "Voltage Selection" (VSEL) pin on V2.x devices. Due to the new technology the core voltage is 1.8 V (see Chapter 1.5).
1.4
Package
In addition to the P-TQFP-144-8 package, a P-BGA-160-1 package with a ball pitch of 1.0 mm and a size of 15 mm x 15 mm is supported (see Figure 4).
1.5
Power Supply
The Version 2.1 device requires two supply voltages, 3.3 V and 1.8 V. For compatibility reasons, it is possible to operate the device off a single 3.3 V supply, with the 1.8 V
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QuadFALC(R) PEF 22554
Overview supply being generated internally using an on-chip voltage regulator. In order to minimize power consumption, it is also possible to operate the device using separate external 3.3 V and 1.8 V supplies. Please note that the 1.8 V supply requires de-coupling whether generated on-chip or externally. Supply voltage selection is done by using pin VSEL. See Figure 1 and Figure 2.
*
3.3 V VDD VDDX VDDR VDDP VDDC VDDC VSS VSSP VSSX VSSR VSEL
3.3 V
VDD, VDDP, VDDX, VDDR > VDDC must always be guaranteed, also during power on and power down sequences.
(can be left open)
QuadFALC(R)
F0248
Figure 1
*
Single Voltage Supply
1.8 V 3.3 V
VDD VDDX VDDR VDDP VDDC VDDC VDD, VDDP, VDDX, VDDR > VDDC must always be guaranteed, also during power on and power down sequences.
VSEL
QuadFALC(R) VSS VSSP VSSX VSSR
F0249
Figure 2
Delta Sheet
Dual Voltage Supply
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Overview
1.6
Pinout
XL1_1/XDOP1/XOID1 VDDX XL2_1/XDON1/XFM1 TDI TDO VDDR RL1_1/RDIP1/ROID1 RL2_1/RDIN1/RCLKI1 VSSR VDDC RCLK1 XPA1 XPB1 XPC1 XPD1 VDDP VSS XPA2 XPB2 XPC2 XPD2 RCLK2 TRS VDDP MCLK VSEL VSSP VSSR RL2_2/RDIN2/RCLKI2 RL1_2/RDIP2/ROID2 VDDR TCK TMS XL2_2/XDON2/XFM2 VDDX XL1_2/XDOP2/XOID2
108 109
VSSX D15 D14 D13 D12 D11 VSS VDD D10 D9 D8 D7 D6 D5 D4 D3 VSS VDD D2 D1 D0 BHE/BLE CS RD/DS WR/RW A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 VSSX
104 100 96 92 88 84 80 76 73 72
112 68
116 64
120 60
124
128
QuadFALC(R) PEF 22554 V2.1
56
52
132 48
136 44
140 40
144 1
4
8
12
16
20
24
28
32
37 36
XL1_4/XDOP4/XOID4 VDDX XL2_4/XDON4/XFM4 SEC/FSC IM VDDR RL1_4/RDIP4/ROID4 RL2_4/RDIN4/RCLKI4 VSSR VDDC ALE RCLK4 XPD4 XPC4 XPB4 XPA4 VSS VDD XPD3 XPC3 XPB3 XPA3 SCLKX4 XDI4 SYNC RCLK3 RES VSSR RL2_3/RDIN3/RCLKI3 RL1_3/RDIP3/ROID3 VDDR INT DBW XL2_3/XDON3/XFM3 VDDX XL1_3/XDOP3/XOID3
VSSX XDI1 SXLKX1 RPA1 RPB1 RPC1 RPD1 SCLKR1 RDO1 VDD VSS RDO2 SCLKR2 RPA2 RPB2 RPC2 RPD2 XDI2 SCLKX2 XDI3 SCLKX3 RPA3 RPB3 RPC3 RPD3 SCLKR3 RDO3 VDD VSS RDO4 SCLKR4 RPA4 RPB4 RPC4 RPD4 VSSX
F0213
Figure 3
Pin Configuration P-TQFP-144-8, Top View
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Overview
1 A B C D E F G H J K L M N P
VSSX
2
3
4
5
6
7
8
9
10
11
12
13
14
XL1_2 XL2_2 VDDR VSSR RL1_2 RL2_2 RL2_1 RL1_1 VSSR VDDR XL2_1 XL1_1
VSSX
XDI1 SCLKX 1 RPB1
MCLK
XPC2
TRS
XPD2
VDD
XPA1
VDDP
XPB1
D15
VSSX
VSSX
VDDX VDDX
TCK
VSSP
VDDP
XPA2
XPB2
XPC1
VDDC
TDO
D14
VDDX VDDX
RPC1
RPA1 SCLKR 1 VSS
RPD1
TMS
VSEL RCLK2
VSS
XPD1 RCLK1
TDI
D12
D13
D11
RDO1
VDD
VDD
VSS
VDD
VDD
D10
RDO2
SCLKR RPA2 2 SCLKX RPD2 2 XDI2 RPA3 SCLKR 3 RDO4 SEC/ FSC VDDC VSS VSS
D9
D7
D8
D6
RPC2
RPB2 SCLKX 3 RPD3
D5
VDD
D4
D3
XDI3
VSS
VSS
D2 BHE/ BLE A9
VSS
D0 W R/ RW A6
D1
RPB3
RPC3
CS
RD/DS
RDO3
VSS
VDD
A8
A7
SCLKR RPB4 4 VDDX VDDX
RPA4
DBW
RCLK3 XPA3 SCLKX 4 SYNC
XPD3
XPB4
ALE
A5
A3
A2
A4
RPC4
INT
RES
VDD
VDD
XPD4
IM
A1
VDDX VDDX
VSSX
VSSX
RPD4
XDI4
XPC3
XPB3
XPA4 RCLK4
VSS
XPC4
A0
VSSX
VSSX
XL1_3 XL2_3 VDDR VSSR RL1_3 RL2_3 RL2_4 RL1_4 VSSR VDDR XL2_4 XL1_4
F0213_2
Figure 4
Ball Layout P-BGA-160-1, Top View
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Overview
14 A B C D E F G H J K L M N P
VSSX
13
12
11
10
9
8
7
6
5
4
3
2
1
XL1_1 XL2_1 VDDR VSSR RL1_1 RL2_1 RL2_2 RL1_2 VSSR VDDR XL2_2 XL1_2
VSSX
D15
XPB1
VDDP
XPA1
VDD
XPD2
TRS
XPC2
MCLK
XDI1
VSSX
VSSX
VDDX VDDX
D14
TDO
VDDC
XPC1
XPB2
XPA2
VDDP
VSSP
TCK
SCLKX VDDX VDDX 1 RPB1 RPA1 RPC1
D11
D13
D12
TDI
RCLK1 XPD1
VSS
RCLK2 VSEL
TMS
RPD1
D10
VDD
VDD
VSS
VDD
VDD SCLKR 2
SCLKR RDO1 1 VSS RDO2
D6
D8
D7
D9
RPA2
D3
D4
VDD
D5
VSS
VSS
RPD2
SCLKX RPB2 2 XDI2 SCLKX 3 RPD3
RPC2
D1
D0 W R/ RW A6
VSS
D2 BHE/ BLE A9 SEC/ FSC VDDC
VSS
VSS
RPA3
XDI3
RD/DS
CS
SCLKR RPC3 3 RDO4 VDD
RPB3
A7
A8
VSS
RDO3 SCLKR 4
A4
A2
A3
A5
ALE
XPB4
XPD3
XPA3 RCLK3 DBW SCLKX 4 SYNC
RPA4
RPB4
VDDX VDDX
A1
IM
XPD4
VDD
VDD
RES
INT
RPC4
VDDX VDDX
VSSX
VSSX
A0
XPC4
VSS
RCLK4 XPA4
XPB3
XPC3
XDI4
RPD4
VSSX
VSSX
XL1_4 XL2_4 VDDR VSSR RL1_4 RL2_4 RL2_3 RL1_3 VSSR VDDR XL2_3 XL1_3
F0213_3
Figure 5
Ball Layout P-BGA-160-1, Bottom View
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Overview
1.7
Table 1 VSEL
Pin Description
Additional Pin Functions I + PU Voltage Select Enables the internal voltage regulator for 3.3 V-only operation mode if connected to VDD (recommended) or left open. Disables the internal voltage regulator for dual power supply mode if connected to VSS. Positive Power Supply for the digital core (1.8 V) These pins can either be positive power supply input or output depending on the VSEL input condition. If the VSEL pin is connected to VSS, these pins are inputs and must both be connected to the same 1.8 V power supply and require decoupling. If the VSEL pin is connected to VDD (3.3 V), these pins will both be 1.8 V power supply outputs and must be decoupled to VSS. Attention: These pins must not be used to supply external devices.
VDDC
S
VDDP
S S
Positive Power Supply for the analog PLL (3.3 V) Power Supply Ground for the analog PLL (0 V)
VSSP
A short pin list of the BGA package is given in Table 2. For a complete signal description refer to the QuadFALC(R) V2.1 Preliminary Data Sheet. Table 2 Ball No. BGA N12 M12 L13 L12 L14 L11 K13 K14 BGA Pin Assignment Pin No. TQFP 74 75 76 77 78 79 80 81 Symbol Input(I) Function Output(O) Supply(S) I + PU I + PU I + PU I + PU I + PU I + PU I + PU I + PU Address Bus Address Bus Address Bus Address Bus Address Bus Address Bus Address Bus Address Bus
A0 A1 A2 A3 A4 A5 A6 A7
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Overview Table 2 Ball No. BGA K12 K11 B12 C12 D13 D12 D14 E14 F11 F13 F12 F14 G11 G13 G14 H11 H14 H13 L9 J14 J13 L4 M11 J12 J11 M4 A9
Delta Sheet
BGA Pin Assignment (cont'd) Pin No. TQFP 82 83 107 106 105 104 103 100 99 98 97 96 95 94 93 90 89 88 62 85 84 40 68 86 87 41 115 Symbol Input(I) Function Output(O) Supply(S) I + PU I + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I + PU I + PU I + PU I + PU I + PU I + PU I + PU O/oD I (analog)
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A8 A9 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ALE RD/DS WR/RW DBW IM CS BHE/BLE INT RL1.1
Address Bus Address Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Address Latch Enable Read Enable Data Strobe Write Enable Read/Write Enable Data Bus Width Interface Mode Chip Select Bus High Enable Bus Low Enable Interrupt Request Line Receiver 1, Channel 1
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Overview Table 2 Ball No. BGA A6 P6 P9 A8 A7 P7 P8 A13 A2 P2 P13 A12 A3 P3 P12 B4 N6 L10 BGA Pin Assignment (cont'd) Pin No. TQFP 138 43 66 116 137 44 65 109 144 37 72 111 142 39 70 133 48 69 Symbol Input(I) Function Output(O) Supply(S) I (analog) I (analog) I (analog) I (analog) I (analog) I (analog) I (analog) Line Receiver 1, Channel 2 Line Receiver 1, Channel 3 Line Receiver 1, Channel 4 Line Receiver 2, Channel 1 Line Receiver 2, Channel 2 Line Receiver 2, Channel 3 Line Receiver 2, Channel 4
RL1.2 RL1.3 RL1.4 RL2.1 RL2.2 RL2.3 RL2.4 XL1.1 XL1.2 XL1.3 XL1.4 XL2.1 XL2.2 XL2.3 XL2.4 MCLK SYNC SEC/FSC
O (analog) Transmit Line 1, Channel 1 O (analog) Transmit Line 1, Channel 2 O (analog) Transmit Line 1, Channel 3 O (analog) Transmit Line 1, Channel 4 O (analog) Transmit Line 2, Channel 1 O (analog) Transmit Line 2, Channel 2 O (analog) Transmit Line 2, Channel 3 O (analog) Transmit Line 2, Channel 4 I I + PU I/O + PU Master Clock Clock Synchronization of DCO-R One-Second Timer Input One-Second Timer Output 8 kHz Frame Synchronization Output Receive Clock, Channel 1 Receive Clock, Channel 2 Receive Clock, Channel 3 Receive Clock, Channel 4 Receive Data Out, Channel 1 Receive Data Out, Channel 2 Receive Data Out, Channel 3 Receive Data Out, Channel 4 System Clock Receive, Ch. 1
D10 D7 L5 N9 E1 F1 K1 K4 E2
119 130 47 61 9 12 27 30 8
RCLK1 RCLK2 RCLK3 RCLK4 RDO1 RDO2 RDO3 RDO4 SCLKR1
O + PU O + PU O + PU O + PU O O O O I/O + PU
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Overview Table 2 Ball No. BGA F3 J4 L1 D2 F4 H4 L3 D3 G2 J1 L2 D1 G1 J3 M3 D4 G4 J2 N3 B3 H3 H1 N4 C3 G3 H2 M6 B9 C7
Delta Sheet
BGA Pin Assignment (cont'd) Pin No. TQFP 13 26 31 4 14 22 32 5 15 23 33 6 16 24 34 7 17 25 35 2 18 20 49 3 19 21 50 120 126 Symbol Input(I) Function Output(O) Supply(S) I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I I I I I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU
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SCLKR2 SCLKR3 SCLKR4 RPA1 RPA2 RPA3 RPA4 RPB1 RPB2 RPB3 RPB4 RPC1 RPC2 RPC3 RPC4 RPD1 RPD2 RPD3 RPD4 XDI1 XDI2 XDI3 XDI4 SCLKX1 SCLKX2 SCLKX3 SCLKX4 XPA1 XPA2
System Clock Receive, Ch. 2 System Clock Receive, Ch. 3 System Clock Receive, Ch. 4 Receive Multifunction Port A, Ch. 1 Receive Multifunction Port A, Ch. 2 Receive Multifunction Port A, Ch. 3 Receive Multifunction Port A, Ch. 4 Receive Multifunction Port B, Ch. 1 Receive Multifunction Port B, Ch. 2 Receive Multifunction Port B, Ch. 3 Receive Multifunction Port B, Ch. 4 Receive Multifunction Port C, Ch. 1 Receive Multifunction Port C, Ch. 2 Receive Multifunction Port C, Ch. 3 Receive Multifunction Port C, Ch. 4 Receive Multifunction Port D, Ch. 1 Receive Multifunction Port D, Ch. 2 Receive Multifunction Port D, Ch. 3 Receive Multifunction Port D, Ch. 4 Transmit Data In, Channel 1 Transmit Data In, Channel 2 Transmit Data In, Channel 3 Transmit Data In, Channel 4 System Clock Transmit, Ch. 1 System Clock Transmit, Ch. 2 System Clock Transmit, Ch. 3 System Clock Transmit, Ch. 4 Transmit Multifunction Port A, Ch. 1 Transmit Multifunction Port A, Ch. 2
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QuadFALC(R) PEF 22554
Overview Table 2 Ball No. BGA L6 N8 B11 C8 N7 L8 C9 B5 N5 N11 D9 B7 L7 M9 B6 D11 D5 C4 C11 M5 D6 A11 A4 P4 P11 A10 A5 P5 P10
Delta Sheet
BGA Pin Assignment (cont'd) Pin No. TQFP 51 57 121 127 52 58 122 128 53 59 123 129 54 60 131 112 141 140 113 46 134 114 139 42 67 117 136 45 64 Symbol Input(I) Function Output(O) Supply(S) I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I/O + PU I + PU I + PU I + PU I + PU O I I + PU S S S S S S S S
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XPA3 XPA4 XPB1 XPB2 XPB3 XPB4 XPC1 XPC2 XPC3 XPC4 XPD1 XPD2 XPD3 XPD4 TRS TDI TMS TCK TDO RES VSEL VDDR VDDR VDDR VDDR VSSR VSSR VSSR VSSR
Transmit Multifunction Port A, Ch. 3 Transmit Multifunction Port A, Ch. 4 Transmit Multifunction Port B, Ch. 1 Transmit Multifunction Port B, Ch. 2 Transmit Multifunction Port B, Ch. 3 Transmit Multifunction Port B, Ch. 4 Transmit Multifunction Port C, Ch. 1 Transmit Multifunction Port C, Ch. 2 Transmit Multifunction Port C, Ch. 3 Transmit Multifunction Port C, Ch. 4 Transmit Multifunction Port D, Ch. 1 Transmit Multifunction Port D, Ch. 2 Transmit Multifunction Port D, Ch. 3 Transmit Multifunction Port D, Ch. 4 Test Reset for Boundary Scan Test Data Input Test Mode Select Test Clock Test Data Output Reset Voltage Select Power Supply for analog receiver 1 Power Supply for analog receiver 2 Power Supply for analog receiver 3 Power Supply for analog receiver 4 Ground for analog receiver 1 Ground for analog receiver 2 Ground for analog receiver 3 Ground for analog receiver 4
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QuadFALC(R) PEF 22554
Overview Table 2 Ball No. BGA BGA Pin Assignment (cont'd) Pin No. TQFP Symbol Input(I) Function Output(O) Supply(S) S S S S S S S S S S S S S S S S S S S S S S S S S S Power Supply for analog transmitter 1 Power Supply for analog transmitter 2 Power Supply for analog transmitter 3 Power Supply for analog transmitter 4 Ground for analog transmitter 1 Ground for analog transmitter 2 Ground for analog transmitter 3 Ground for analog transmitter 4 Pad Power Supply 3.3 V Pad Power Supply 3.3 V Pad Power Supply 3.3 V Pad Power Supply 3.3 V Pad Power Supply 3.3 V Pad Power Supply 3.3 V Analog PLL Power Supply 3.3 V Analog PLL Power Supply 3.3 V Core Power Supply 1.8 V Core Power Supply 1.8 V Ground for analog PLL Ground Ground Ground Ground Ground Ground Ground
C13, C14 110 C1, C2 M1, M2 M13, M14 B1, B2 N1, N2 E3, E4 K3 M7, M8 G12 B8 B10 C6 M10 C10 C5 F2 K2 N10 H12 E11 D8 G7, G8, H7, H8 143 38 71
VDDX VDDX VDDX VDDX VSSX VSSX VSSX VSSX VDD VDD VDD VDD VDD VDD VDDP VDDP VDDC VDDC VSSP VSS VSS VSS VSS VSS VSS VSS
B13, B14 108 1 36 10 28 55 91 --124 132 63 118 135 11 29 56 92 102 125 ---
N13, N14 73
E12, E13 101
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Overview
1.8
Decoupling Capacitors
To gain best performance, the following values are recommended for the external decoupling capacitors between VDDC and VSS. There is one decoupling capacitor required on each VDDC pin. Table 3 Parameter Capacitance Capacitor material ESR Loop inductance (LL) between VDDC, capacitor and next VSS pin Decoupling Capacitor Parameters Value 470 nF 20 %, alternatively: 2 x 220 nF 20 % ceramic, type X7R or compatible < 30 m < 10 nH
118
VDDC
VDDC 63
LL VDD VSS VSS VDD
56
LL
125
F0252
Figure 6
Decoupling Capacitor Placement
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Overview
1.9
Operation Description E1/T1/J1
Note: Write access to unused register addresses: should be avoided, or set to "00" hex in address range. up to xA9; must be avoided in address range above xA9 if not defined elsewhere (for example in Table 4). To achieve optimum receiver sensitivity in E1 long haul mode (> 38 dB) the following sequence must be run: Table 4 Address BBH BCH BBH BBH BCH BBH BBH BCH BBH BBH BCH BBH Receive Line Interface Initialization (E1) Data 17H 55H 97H 11H AAH 91H 12H 55H 92H 0CH 00H 8CH
Note: Sequence must be repeated whenever receiver reset (CMDR.RRES) of arbitrary channel was performed (e.g. after setting bit LIM1.EQON).
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Overview
1.10
Device Marking Pattern
The sales code changed from PEB 22554 Version 1.3 to PEF 22554 Version 2.1. The new marking pattern is:
Engineering Samples PTQFP:
Final Devices PTQFP:
PEF 22554 HT V2.1 QuadFALC ES A21
PEF 22554 HT V2.1 QuadFALC A21
Engineering Samples PBGA:
Final Devices PBGA:
PEF 22554 E V2.1 QuadFALC ES A21
PEF 22554 E V2.1 QuadFALC A21
F0200
Figure 7
Marking Pattern
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1.11
Flexible Clock Mode Settings
The register settings for flexible master clock can be calculated as follows. For some standard frequencies see Table 5 below. The variables used in these calculations are located in registers GCM1 to GCM8. 1. PLL_M and PLL_N must fulfill the equations: a. for PLL_M = 0 to 31:
f MCLK f pdref = --------------------------PLL_M + 1
b. for PLL_N = 25 to 63:
1.0 MHz f pdref 6.0 MHz
for PLL_N = 0 to 24:
5.0 MHz f pdref 15.0 MHz
Attention: To decrease sensitivity of PLL to noise on VDDP and/or VSSP adjust fpdref as high as possible. c.
4 x ( PLL_N + 1 ) 260 MHz f MCLK x ---------------------------------------- 395.26 MHz PLL_M + 1
(as high as possible within this range) 2. Selection of dividing mode to best fulfill:
4 x ( PLL_N + 1 ) f outE1 = f MCLK x ---------------------------------------------------------------------------------------------------- 2 x 16.384 MHz ae PHSN_E1 + PHSX_E1o x ( PLL_M + 1 ) -----------------------e o 6 4 x ( PLL_N + 1 ) f outT1 = f MCLK x ---------------------------------------------------------------------------------------------------- 2 x 12.352 MHz PHSX_T1o ae PHSN_T1 + ------------------------ x ( PLL_M + 1 ) e o 6
Though the target frequency might not be met directly, the dividing mode has to be selected to reach a frequency which is as near as possible to the target frequency.
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QuadFALC(R) PEF 22554
Overview PHSN_E1, PHSN_T1: 1 to 15; PHSX_E1, PHSX_T1: 0 to 5
3. Calculation of correction value for frequency mismatch correction:
f MCLK PHSX_E1 4 x ( PLL_N + 1 ) PHD_E1 = 12288 x ae PHSN_E1 + ------------------------o - ---------------------------------------- x -------------------------------------e o 2 x 16.384 MHz 6 PLL_M + 1 f MCLK PHSX_T1 4 x ( PLL_N + 1 ) PHD_T1 = 12288 x ae PHSN_T1 + ------------------------o - ---------------------------------------- x -------------------------------------e o 6 2 x 12.352 MHz PLL_M + 1
The result of these equations will be in the range of -2048...+2047. Negative values are represented in 2s-complement format (e.g., -2000D = 830H ; +2000D = 7D0H). To achieve optimal QuadFALC(R) performance values < -1023 and > +1023 must be applied. Negative values are favored. Table 5 fMCLK[MHz] 1.544 2.048 8.192 10.000 12.352 16.384 Clock Mode Register Settings for E1 and T1/J1 GCM1 00 00 00 40 00 00 GCM2 15 18 18 1B 19 18 GCM3 00 FB FB 3D 00 FB GCM4 08 0B 0B 0A 08 0B GCM5 00 00 00 00 01 01 GCM6 3F 2F 0B 07 0A 0B GCM7 9C DB DB C9 98 DB GCM8 DF DF DF DC DA DF
Note: All values are given in hexadecimal notation. To support the necessary calculations, an easy-to-use PC tool is available for free (see Page 29 for details).
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1.12
Register Modifications
Framer Mode Register 2 (Read/Write) Value after reset: 00H
7
FMR2 AFRS MCSP SSP DAIS SAIS PLB AXRA
0
EXZE (x1E)
AFRS
Automatic Force Resynchronization Search for next candidate automatically, if multiple candidates are present and the current candidate is incorrect. (This bit is available in T1/J1 F12 mode only).
Line Interface Mode 2 (Read/Write) Value after reset: 20H
7
LIM2 LBO2 LBO1 SLT1 SLT0 SCF ELT
0
LOS1 (x3A)
LBO(2:0)
Line Build-Out To meet the line build-out defined by ANSI T1.403 registers XPM(2:0) should be programmed as follows: 00 01 10 11 0 dB -7.5 dB -15 dB
XPM(2:0) = 00H, 01H, 8CH XPM(2:0) = 01H, 11H, 8CH
-22.5 dB XPM(2:0) = 00H, 01H, 07H
(This bits are available in T1/J1 mode only).
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QuadFALC(R) PEF 22554
Overview Line Interface Mode 0 (Read/Write) Value after reset: 00H
7
LIM0 XFB XDOS 0 0 EQON RLM LL
0
MAS (x36)
EQON
By setting EQON = 1 the QuadFALC(R) is able to adjust short haul or long haul mode automatically. After changing the value of EQON a receiver reset (CMDR.RRES) is required. For E1 mode please note sequence as specified in Table 4 on Page 14.
Note: When using EQON = 1 together with RLM = 1, LIM1.RIL(2:0) must be set to 001B. Line Interface Mode 1 (Read/Write) Value after reset: 00H
7
LIM1 CLOS RIL2 RIL1 RIL0 JATT RL
0
DRS (x37)
DRS
Dual Rail Select Note: LIM0.EQON must be set to 0 when DRS = 1
Version Status Register (Read)
7
VSTR 0 0
0
0 0 0 1 0
1 (4A)
VN(7:0)
Version Number of Chip 05H...Version 2.1
Port Configuration 5 (Read/Write) Value after reset: 20H
7
PC5 CXMFS 0 CSRP
0
CRP (x84)
PC5.2
reserved Must be cleared.
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QuadFALC(R) PEF 22554
Overview Common Configuration Register 5 (Read/Write) Value after reset: 00H
7
CCR5
1)
0
CSF2 SUET CSF AFX CR1) EPR1) (x8D)
T1 mode only
CSF2
Compare Status Field - Mode 2 If the status fields of consecutive LSSUs are equal, only the first is stored and every following is ignored. Exception: if identical FISUs are received, two of them are stored, 0 1 Compare disabled. Compare enabled.
Note: Only valid if SS7 is selected Global Clock Mode Register 2 (Read/Write) Value after reset: 00H
7
GCM2 0 0 0 1
0
PHD_E1 PHD_E1 PHD_E1 PHD_E1 11 10 9 8 (93)
GCM2(7:5) GCM2(4)
removed bits must be set to 1, details for calculate of the remaining GCM values can be found in Chapter 1.11.
Global Clock Mode Register 4 (Read/Write) Value after reset: 00H
7
GCM4 0 0 0 0
0
PHD_T1 PHD_T1 PHD_T1 PHD_T1 11 10 9 8 (95)
GCM4(7:5)
removed bits
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QuadFALC(R) PEF 22554
Overview Global Clock Mode Register 5 (Read/Write) Value after reset: 00H
7
GCM5 0 0 0
0
PLLM_4 PLLM_3 PLLM_2 PLL_M1 PLL_M0 (96)
GCM5.7
removed bit, to be set to 0
Global Clock Mode Register 6 (Read/Write) Value after reset: 00H
7
GCM6 0 0
0
PLLN_5 PLLN_4 PLLN_3 PLLN_2 PLL_N1 PLL_N0 (97)
GCM6.5
added bit
Attention: Write operations to GCM5 and/or GCM6 register must be performed before any port configuration is done. If this is not possible set LIM0.DRS (if not set) of every channel seperately before writing to these registers and reset LiM0.DRS (if it was not set before) after these write operations. Global Clock Mode Register 7 (Read/Write) Value after reset: 00H
7
GCM7 1 PHSX_ E12 PHSX_ E11 PHSX_ E10 PHSN_ E13 PHSN_ E12 PHSN_ E11
0
PHSN_ E10 (98)
GCM7.7 PHSX_E1(2:0) PHSN_E1(3:0)
added bit, to be set to 1 added bits added bits
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QuadFALC(R) PEF 22554
Overview Global Clock Mode Register 8 (Read/Write) Value after reset: 00H
7
GCM8 1 PHSX_ T12 PHSX_ T11 PHSX_ T10 PHSN_ T13 PHSN_ T12 PHSN_ T11
0
PHSN_ T10 (99)
GCM8.7 PHSX_T1(2:0) PHSN_T1(3:0)
added bit, to be set to 1 added bits added bits
Channel Interrupt Status Register (Read)
7
CIS PLLL 0
0
0
0 GIS4 GIS3 GIS2 GIS1 (6F)
CIS.7
PLL Locked Status 1 if PLL is locked, 0 if PLL is unlocked Note:This bit is only updated when a clock is available on pin MCLK
Transmit Pulse Mask 2...0 (Read/Write) Value after RESET: 7BH, 03H, 40H
7
XPM0 XPM1 XPM2
C
0
XP11 XP24 XLT XP10 XP23 DAXLT XP04 XP22 XP03 XP21 XP34 XP02 XP20 XP33 XP01 XP14 XP32 XP00 XP13 XP31 (x26) (x27) (x28)
XP12 XP30 XLLP
Table 6 Range in m 0 to 40 40 to 81
Pulse Shaper Programming (T1/J1)1) Range in ft. 0 to 133 XPM0 XPM1 XPM2 XP04- XP14XP00 XP10 21 22 20 21 XP24XP20 5 7 XP34XP30 2 3
hexadecimal 95 16 9E 01 01 133 to 266 B6
decimal
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Overview Table 6 Range in m 81 to 122 Pulse Shaper Programming (T1/J1)1) Range in ft. XPM0 XPM1 26 36 CB XPM2 01 01 01 XP04- XP14XP00 XP10 25 28 31 22 23 28 XP24XP20 9 13 18 XP34XP30 2 2 3
266 to 399 D9
122 to 162 399 to 533 FC 162 to 200 533 to 655 3F
1)
Register values of V1.3 may also be used. For optimum results V2.1 values must be applied
Example for E1 120 interface: Programming values for XPM(2:0): 00H, 03H, 9CH. XPM0(4:0): 1CH or 28 decimal XPM1(4:0): 1CH or 28 decimal XPM2(4:0): 00H XPM3(4:0): 00H
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QuadFALC(R) PEF 22554
Electrical Characteristics
2
Electrical Characteristics
Due to the change of silicon technology some of the electrical characteristics have changed.
2.1
Parameter
Absolute Maximum Ratings
Symbol min. Limit Values max. 85 125 3.60 1.98 3.60 3.60 3.60 3.60 2000 500 2254) 2455) - 40 - 65 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 Unit
Ambient temperature under bias Storage temperature IC supply voltage (pads, digital) IC supply voltage (core, digital) IC supply voltage PLL (analog) IC supply voltage receive (analog) IC supply voltage transmit (analog) Voltage on any pin with respect to ground1) ESD robustness HBM: 1.5 k, 100 pF2) CDM 3) Moisture level 3
1) 2) 3) 4) 5)
TA Tstg VDD VDDC VDDP VDDR VDDX VS
C C
V V V V V V V V
VESD,HBM VESD,CDM ---
C C
Except VDDC According to JEDEC standard EIA/JESD22-A114-B-1997. According to EOS/ESD Assn.Standard DS5.3-1993 According to IPS J-STD 020 According to IFX internal standard
Attention: If the 1.8 V power supply is externally driven on VDDC, the voltage on this pin must never exceed the 3.3 V supply voltages on pins VDD, VDDP, VDDX and VDDR, even during power up and power down of the circuit. Attention: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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Electrical Characteristics
2.2
Parameter
Operating Range
Symbol Limit Values min. max. 85 3.46 3.46 3.46 1.98 3.46 3.602) 3.46 0 -40 3.13 3.13 3.13 1.62 3.13 0 0 0 Unit Notes
Ambient temperature Supply voltages
Analog input voltages Digital input voltages Ground
TA VDD VDDP1) VDDR1) VDDC VDDX1) VIA VID VSS VSSP VSSR VSSX
C
V V V V V V V V 3.3 V 5% 3.3 V 5% 3.3 V 5% 1.8 V 10% 3.3 V 5% 3.3 V 5% 3.3 V 5%
1) 2)
Voltage ripple less than 50 mV on these 3.3V supplies Depending on the applied power supply level, signal clipping may occur due to activation of the ESD protection diodes if the signal level exceeds VDDR + 0.3 V
Note: In the operating range, the functions given in the circuit description are fulfilled. VDD, VDDP, VDDR and VDDX have to be connected to the same voltage level, VSS, VSSP, VSSR, and VSSX have to be connected to ground level. VDD and VDDC refer to the same ground level VSS.
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Electrical Characteristics
2.3
Parameter
Changed DC Characteristics
Symbol Limit Values min. max. 3.46 290 285 201) 90 V mA mA mA mA E1 application LIM1.DRS = 0 T1 application LIM1.DRS = 0 LIM1.DRS = 12) 2.0 Unit Notes
Input high voltage Average power supply current (analog line interface mode) Average power supply current (digital line interface mode) Transmitter leakage current
VIH IDDE1 IDDT1 IDD3.3V IDDC ITL
15.0 15.0
A A
dB V
XL1/2 = VDDX; XPM2.XLT = 1 XL1/2 = VSSX; XPM2.XLT = 1 RL1, RL2 LIM0.EQON = 1 RIL(2:0) = 0006) RIL(2:0) = 0016) RIL(2:0) = 0107) RIL(2:0) = 0116) RIL(2:0) = 1006) RIL(2:0) = 1016) RIL(2:0) = 1106) RIL(2:0) = 1116)
Receiver sensitivity E1 long haul Loss of signal (LOS) detection limit4)5)
SRLH VLOS
1.25 0.84 0.45 0.26 0.15 0.10 0.07 0.04
433) 2.25 1.07 0.58 0.33 0.21 0.14 0.09 0.06
1) 2) 3)
In single voltage supply mode (see Figure 1) maximum IDD3.3V = 110 mA System interface at 16 MHz; all-ones data; TA = 85 C To achieve maximum receiver sensitivity of -43 dB (E1) take special care on sufficient attenuation of crosstalk between Rx and Tx on board (e.g. in transformer) and run sequence as specified in Table 4 on Page 14 Differential input voltage between pins RL1 and RL2 Values only valid for LIM0.EQON = 1, LOS detection limits set to PCR = 15H, PCD = AH, applied signal sequence +1,0,-1,0,... Parameter not tested in production Value measured in production to fulfil ITU-T G.775
4) 5)
6) 7)
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QuadFALC(R) PEF 22554
Electrical Characteristics
2.4
Parameter
Changed Supply Power Test Conditions T1/J1
Symbol XPM2 XPM1 XPM0 Test Values 01H 16H 95H Unit Notes
Pulse Mask Programming
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Electrical Characteristics
2.5
Package Outlines
P-BGA-160-1 (Plastic Ball Grid Array Package)
GPA09369
You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. SMD = Surface Mounted Device Delta Sheet 28/30 Dimensions in mm 2002-09-16
QuadFALC(R) PEF 22554
Appendix
3
Appendix
The calculation of the GCM register values is supported by a PC-based tool which is available for free. A screenshot is shown in Figure 8 below.
F0260
Figure 8
Flexible Master Clock Calculator
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QuadFALC(R) PEF 22554
Appendix
F0234
Figure 9
Application Wizard
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